1. Field of the Invention
The present invention is directed to a memory arrangement. The present invention is particularly directed to a dynamic memory arrangement having a memory cell field composed of a plurality of memory cells that respectively comprise at least one selection transistor and a storage capacitor, and can be driven via word lines and bit lines.
2. Description of the Related Art
A dynamic memory arrangement typically comprises a plurality of memory cells. Each memory of these cells contain at least one selection transistor and a storage capacitor. These memory cells are usually arranged in rows and columns and use a plurality of bit lines and word lines in order to designationally address individual memory cells. In traditional memory arrangements, a memory cell can be selected for reading or writing by selecting a bit line and by selecting a word line. These word lines drive the selection transistor such that the selection transistor connects the storage capacitor to the bit line in an electrically conductive fashion. In this way, charge can be stored in the storage capacitor via the bit line or can be read out from the storage capacitor.
Amplifiers are usually employed for reading out the charge stored in a storage capacitor. These amplifiers are arranged at the ends of the bit lines as a rule. Since only extremely small currents flow given a read out of a selected storage capacitor, the amplifiers are usually respectively connected to a pair of bit lines. One of the bit lines then serves as a reference line for the other bit line so that the amplifier can determine information about the charge stored in the selected storage capacitor from the differences between the two bit lines. One of the bit lines is then usually placed at a high potential and the other bit line is placed at a low potential. These lines are therefore referred to as complementary bit lines. The bit lines are usually conducted in a metallization level, and their connection to the diffusion zones of the selection transistors is produced using via holes.
A large part of the outlay in the technology development of dynamic memory arrangements is comprised in generating the storage capacitor. In order to obtain an adequately high signal upon readout of the storage capacitor, the storage capacity of the storage capacitor should amount to at least 35 fF. Since the lateral expanse of the storage capacitor is becoming smaller and smaller at the same time, one is forced to generate more and more complex three-dimensional structures in order to make adequate capacitor area available.
A frequently employed embodiment for such a structure is the xe2x80x9cstacked capacitorxe2x80x9d. Stacked capacitors exist in a number of different configurations, for example, crown stacked capacitors or hemispherical grained stack capacitors. What all of these configurations have in common, however, is that they are arranged above the silicon substrate and above the selection transistors. They thus lie in a region of the memory arrangement in which the bit lines are also arranged. Particularly when pairs of bit lines are employed, it is desirable to arrange the bit lines and the storage capacitors such that an optimally small area is consumed per memory cell and, at the same time, a cost-beneficial production of the memory cell is possible.
This object is inventively achieved by a memory arrangement comprising: a first conductive layer; an insulating layer; a second conductive layer that is separated from the first conductive layer by the insulating layer; a plurality of memory cells, the memory cells each comprising at least one selection transistor; and a stacked capacitor arranged between the first and second conductive layer; the memory arrangement further comprising word lines configured to drive a predetermined plurality of the memory cells; bit lines configured to drive the predetermined plurality of the memory cells, the bit lines comprising at least one first bit line and at least one second bit line, the first bit line and the second bit line being complementary to one another upon a readout of the memory cells, the bit lines being respectively conducted partly in the first conductive layer and the bit lines being connected from there to at least a part of the plurality of memory cells and the bit lines being respectively conducted in part in the second conductive layer, wherein a part of the first bit line or, respectively, a part of the second bit line that is conducted in the first conductive layer and a part of the first bit line or, respectively, a part of the second bit line that is conducted in the second conductive layer are connected to one another through the insulating layer via at least one first contact or, respectively, via at least one second contact; and at least one of the first contact and the second contact are arranged above an active region overlapping with a via hole to one of the memory cells. Further advantageous embodiments, properties and aspects of the present invention are described below.
Inventively, a memory arrangement having a plurality of memory cells is provided that each respectively comprise at least one selection transistor and a stacked capacitor and can be driven via word lines and bit lines. The inventive memory arrangement includes:
a) a first conductive layer
b) a second conductive layer that is separated from the first conductive layer by an insulating layer, and
c) at least one first bit line are provided for a respectively predetermined plurality of memory cells, this bit line being conducted partly in the first conductive layer and being connected from there to at least a part of the memory cells and being conducted in part in the second conductive layer, and
d) the stacked capacitors of the memory cells are arranged between the first and the second conductive layer.
The inventive memory arrangement has the advantage that, due to the arrangement of the stacked capacitors between the first and the second conductive layer, both the aspect ratios of the via holes that connect the first conductive layer to the selection transistors as well as the aspect ratios of the xe2x80x9cplugsxe2x80x9d which connect the storage capacitors to the selection transistors can be kept relatively low. Furthermore, the employment of two conductive layers, for example, two metallization layers, makes it possible to realize bit line concepts that enable a dependable readout of the charge stored in the stacked capacitor even given great noise on the bit lines. Over and above this, the inventive memory arrangement makes it possible to realize memory cells whose lateral expanse is less than or equal to 7F2. F (Feature size) represents the smallest structure width that can be generated by the manufacturing technology employed.
According to a preferred embodiment, a second bit line is provided for the predetermined plurality of memory cells, the second bit line being partly conducted in the first conductive layer and, from this, being connected to at least a part of the memory cells and being conducted partly in the second conductive layer. It is particularly preferred when the bit lines are complementary to one another upon readout of the memory cells.
It is also preferred when the bit lines are connected to an amplifier that reads out the charge that is stored in one of the memory cells.
According to another preferred embodiment, the part of the bit line that is conducted in the first conductive layer and the parts of the first bit line that is conducted in the second conductive layer are connected to one another through the insulating layer via at least one first contact.
It is likewise preferred when the part of the second bit line that is conducted in the first conductive layer and part of the second bit line that is conducted in the second conductive layer are connected to one another via at least one second contact through the insulating layer. It is particularly preferred when the first and second contact are arranged such that the capacitances of the first and of the second bit line are essentially the same for the amplifiers.
According to another preferred embodiment, the first and/or second contact are arranged above the active region. This has the advantage that no additional chip area need be made available for these contact regions. The memory density that can be achieved is correspondingly increased.
It is particularly preferred when the first and/or second contact are arranged overlapping with a via hole to a memory cell. It is also preferred when a landing pad is arranged between the first and/or second contact and the first conductive layer and/or when the first conductive layer comprises a broadened portion in the region of the first and/or second contact.
According to another preferred embodiment, the memory cells are aligned with an angle between 10xc2x0 and 60xc2x0, particularly with an angle between 20xc2x0 and 40xc2x0, relative to the first and/or the second bit line.
It is also preferred when the memory cells are fashioned with a lateral expanse of less than or equal to 7F2.